1. Field of the Invention
The present invention relates to an amplification circuit, to a driver circuit for a display, and to a display. More particularly, the invention relates to an amplification circuit that can be used in a driver circuit for a display. The invention also relates to a driver circuit incorporating the amplification circuit. Furthermore, the invention relates to a display using the driver circuit.
2. Description of the Related Art
In recent years, plasma display panels (PDPs) and liquid crystal divice (LCDs) have become widespread as display devices. Since these liquid crystal displays have features of thinness, lightweightness, and low power consumption, the LCDs are increasingly used especially in so-called mobile terminals such as cell phones, PDAs (personal digital assistances) notebook computers, and portable TV units.
Furthermore, development of large-sized liquid crystal displays is in progress. Applications to non-portable large-screen displays and large-screen TV sets are on the rise.
Of these liquid crystal displays, active-matrix-driven displays which have excellent response speed and image quality and permit high-definition display have become the mainstream. Nonlinear devices such as transistors or diodes are used at each pixel of the display portion of this type of liquid crystal display. An image is displayed on the display portion by activating these devices.
More specifically, the liquid crystal display has a semiconductor substrate and a counter substrate mounted opposite to each other. Transparent pixel electrodes and thin-film transistors (TFTs) are arranged on the semiconductor substrate. One transparent electrode is formed on the whole display portion of the counter substrate. A liquid crystal material is sealed between the two substrates. A voltage corresponding to a pixel gray level is applied to each pixel electrode to produce a voltage difference between each pixel electrode and the electrode of the counter substrate by controlling the TFTs having a switching function. In this way, the transmittance of the liquid crystal material is varied, and an image is displayed.
Plural data lines for applying voltages (hereinafter referred to as the gray level voltages) corresponding to gray levels to the pixel electrodes are arranged on the semiconductor substrate. Scanning lines for applying control signals for turning on and off the TFTs are arranged also on the semiconductor substrate. Application of the gray level voltage to the pixel electrodes is done via the data lines. An image is displayed on the display portion of the LCD by applying gray level voltages to all the pixel electrodes connected to the data lines during one frame period for image display.
The data lines provide large capacitive load due to the capacitance of the liquid crystal material sandwiched between the opposite substrate electrodes and due to capacitance produced at the intersections of scanning lines when viewed from the driver circuit (hereinafter may also be referred to as the source driver) for applying the gray level voltages.
Therefore, a driver circuit for driving these data lines is required to drive the data lines having large capacitive load at high voltage accuracy and at high speed. To satisfy this requirement, various data line driver circuits have been developed (see, for example, JP-A-2001-42287 (patent reference 1)).
An example of such a data line driver circuit is hereinafter described in detail by referring to a drawing. Higher accuracy and higher speed are imparted to this data line driver circuit by an operational amplifier 100 used as an output amplifier. FIG. 8 schematically shows the configuration of the operational amplifier 100 used as the output amplification circuit of the data line driver circuit.
As shown in FIG. 8, the operational amplifier (op amp) 100 is a voltage follower operational amplifier apparatus including a differential amplifier 110 and an output amplifier 120. This operational amplifier apparatus 100 outputs a voltage its output terminal Vo, the voltage being equal to the voltage at its input terminal Vin.
The differential amplifier 110 includes a constant current circuit I100, PMOS transistors T100 and T101 having the same characteristics, and NMOS transistors T102, T103 having the same characteristics.
The constant current circuit I100 is connected between a first potential (Vcc in this example) and the common source of the PMOS transistors T100, T101. The sources of the PMOS transistors T100 and T101 are connected together.
The gate of the PMOS transistor T100 is connected to the input terminal Vin, while the drain is connected to the drain of the NMOS transistor T102. The drain of the PMOS transistor T101 is connected to the drain of the NMOS transistor T103, whereas the gate is connected to the output terminal Vo.
The sources of the NMOS transistors T102 and T103 are both connected to a second potential (GND in this example). The gates of the NMOS transistors T102 and T103 are both connected to the drain of the NMOS transistor T103.
Meanwhile, the output amplifier 120 includes a constant current circuit I101, an NMOS transistor T105, and a capacitive device C100.
The constant current circuit I101 is connected between the first potential and the output terminal Vo. The drain of the NMOS transistor T105 is connected to the output terminal Vo, whereas the source is connected to the second potential. The gate of the NMOS transistor T105 is connected to the drain of the PMOS transistor T100 and to the drain of the NMOS transistor T102. The capacitive device C100 is mounted as a capacitor for providing phase compensation, and is connected between the drain and gate of the NMOS transistor T105.
Let I100 be the current limited by the constant current circuit I100. Let I101 be the current limited by the constant current circuit I101. It is assumed that a data line having a capacitive load is connected to the output terminal Vo.
In this way, in the operational amplifier apparatus 100, the voltage at the output terminal Vo is fed back to the differential amplifier 110, i.e., applied to the gate of the PMOS transistor T101. The operational amplifier apparatus 100 has a voltage amplification factor of 1, and forms a voltage follower having high current supply capabilities. The operation of the operational amplifier apparatus 100 designed in this way is described in detail below.
When the voltage at the output terminal Vo of the op amp apparatus 100 is lower than the voltage at the input terminal Vin, the gate voltage of the NMOS transistor T105 is lowered, turning off the NMOS transistor T105 temporarily. Consequently, the voltage at the output terminal Vo is pulled up by the current I101 from the constant current circuit I101.
Meanwhile, when the voltage at the output terminal Vo is higher than the voltage at the input terminal Vin, the gate voltage of the NMOS transistor T105 is pulled up. The voltage at the output terminal Vo is pulled down by the NMOS transistor T105. At this time, the PMOS transistors T100 and T101 act in such a way that the electrical current flowing between the source and drain of T100 is equal to the electrical current flowing between the source and drain of T101 and so the voltage at the output terminal Vo quickly converges to the voltage level at the input terminal Vin while attenuating.
In this way, in the operational amplifier apparatus 100, even where an input signal is applied to the input terminal Vin while switching the gray level voltage for the pixels sequentially, data lines connected to the output terminal Vo and having capacitive load can be driven at high speed by a gray level voltage at high voltage accuracy and with high current supply capabilities.